Seminars by Dr. Yong Ching Lim, Scaling the Sidelobe Magnitude of Fixed Classical Beamformer & Prof. Yajun Ha, Energy Efficient Edge Computing for Smart Applications in the Post-Moore Era (16 Feb 2024)

16 Feb 2024 02.30 PM - 04.30 PM Current Students, Industry/Academic Partners

You are cordially invited to the seminar jointly organized by
 
IEEE Circuits and Systems Singapore Chapter &
IEEE Signal Processing Singapore Chapter & 
IEEE Industrial Electronics Society Singapore Chapter &
Centre for Information Sciences and Systems (CISS), School of EEE, NTU 

Date and Time:

16 Feb 2024 (Fri) | 2:30pm – 4:30pm

Venue:

NTU EEE Executive Seminar Room (S2.2-B2-53)

 

Seminar 1:

Title: Scaling the Sidelobe Magnitude of Fixed Classical Beamformer

Speaker: Dr. Yong Ching Lim, IEEE Life Fellow

Abstract:

The peak sidelobe magnitudes of some classical phased array beamformer such as the Hamming and Blackman beamformers are fixed and are not adjustable. Presented in this talk is a method for adjusting the peak sidelobe magnitudes of any beamformer including the fixed non-adjustable beamformers. The method involves expressing the array factor in terms of a variable x in the form of Chebyshev polynomial of the first kind followed by scaling of the x-axis. This talk is derived from one of the speaker’s papers published in a 2021 issue of IEEE Signal Processing Letters.

Biography:

Dr Lim’s research interests focus on (1) signal processing for implementation on silicon and (2) phased array beamformer. Dr Lim is recipient of (1) the 1996 IEEE Circuits and Systems Society's Guillemin-Cauer best paper award for one of his papers published in IEEE Trans. on CAS and (2) the 1990 IREE (Australia) Norman Hayes Memorial best paper award for one of his papers published in the Journal of Electrical and Electronics Engineering (Australia). Dr Lim is a Life Fellow of the IEEE. He served as a distinguished lecturer in IEEE CAS Society’s distinguished lectures program from January 2001 to December 2002. He had served as Editor and Associate Editor of various journals and General-chair of several international conferences. Before his retirement from the universities in 2018, he taught courses on digital and analogue integrated circuit design, digital signal processing, and computer architecture.

Lim Yong Ching was born in 1953 in Malaysia. He was awarded an ASEAN scholarship to continue his upper secondary education in Singapore. He read electrical engineering in Imperial College, London, and was awarded the Siemens Memorial Award for being the top student in the entrance examination. He was awarded the 1977 IEE prize for being the student with the best all-round performance in the final year examination. He continued to read PhD in Imperial on a University of London studentship. After his graduation from Imperial, Dr Lim served in (1) Naval Postgraduate School (California), (2) National University of Singapore (Singapore) and (3) Nanyang Technological University (Singapore).

 

Seminar 2:

Title: Energy Efficient Edge Computing for Smart Applications in the Post-Moore Era

Speaker: Prof. Yajun Ha, ShanghaiTech Unversity, Editor-in-Chief, IEEE TCAS-II

Abstract:

Smart applications such as robot and advanced driver assistance have significantly made our life easier and better. For the sake of various constraints such as real time, many of these applications involve computing in mobile edge devices. These devices are usually powered by batteries that require energy efficient computing to enable longer interval between the charging of batteries. On the other hand, new semiconductor technology (such as non-volatile memories, cryogenic microelectronics) and new computing paradigm (such as in-memory computing and neural network computing) have been actively researched to support energy efficient computing.

Under this background, this talk introduces the on-going research works in the Smart and Reconfigurable Computing Lab, ShanghaiTech University. In terms of applications, we have focused on the area of robot and smart vehicles. In terms of circuit/semiconductor technologies, we have focused on RRAM, cryogenic CMOS, near/sub-threshold low voltage circuit designs. In terms of computing paradigm, we have focused on SRAM-based in-memory computing and FPGA acceleration of neural networks. We have also built an FPGA research platform and a smart vehicle research platform. They enable us to interact these above topics and perform interdisciplinary research and prototyping.

Biography:

Yajun Ha received the B.S. degree from Zhejiang University, Hangzhou, China, in 1996, the M.Eng. degree from the National University of Singapore, Singapore, in 1999, and the Ph.D. degree from Katholieke Universiteit Leuven, Leuven, Belgium, in 2004, all in electrical engineering. He is currently a Professor at ShanghaiTech University, China. Before this, he was a Scientist and Director, I2R-BYD Joint Lab at Institute for Infocomm Research, Singapore, and an Adjunct Associate Professor at the Department of Electrical & Computer Engineering, National University of Singapore. Prior to this, he was an Assistant Professor with National University of Singapore. His research interests are focused on energy efficient circuits and systems, including reconfigurable computing, ultra-low power digital circuits and systems, embedded system architecture and design tools for applications in robots, smart vehicles and intelligent systems. He has published more than 130 internationally peer-reviewed journal/conference papers on these topics. He is the recipient of 2021 NSFC Senior Foreign Scholar Fund.

He has served a number of positions in the professional communities. He serves as the Editor-in-Chief for the IEEE Trans. on Circuits and Systems II: Express Briefs (2022–2023), Associate Editor-in-Chief for the IEEE Trans. on Circuits and Systems II: Express Briefs (2020–2021), the Associate Editor for the IEEE Trans. on Circuits and Systems I: Regular Papers (2016–2019), the Associate Editor for the IEEE Trans. on Circuits and Systems II: Express Briefs (2011–2013), the Associate Editor for the IEEE Trans. on Very Large Scale Integration (VLSI) Systems (2013–2014), and the Journal of Low Power Electronics (since 2009). He has served as the TPC Co-Chair of ISICAS 2020, the General Co-Chair of ASP-DAC 2014; Program Co-Chair for FPT 2010 and FPT 2013; Chair of the Singapore Chapter of the IEEE Circuits and Systems (CAS) Society (2011 and 2012); Member of ASP-DAC Steering Committee; and Member of IEEE CAS VLSI and Applications Technical Committee. He has been the Program Committee Member for a number of well-known conferences in the fields of FPGAs and design tools, such as DAC, DATE, ASP-DAC, FPGA, FPL and FPT. He is the recipient of several IEEE/ACM Best Paper Awards. He is a senior member of IEEE.

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