Wire Bond Interconnects for Advanced Silicon Process Technologies

The microelectronic industry continues to make great strides in integration and functionality resulting in doubling of microprocessor clock-speeds every two years. New and innovative materials and processes in wafer fabrication and packaging have brought about this amazing accomplishment. Enabled by the now pervasive giga-scale integration, the transistor continues to shrink to under 100nm dimensions and pin counts of ASIC devices continue to expand beyond 500-2,000 I/O's pushing the interconnect pitches to under 45um.

Advanced silicon processes such as the Cu-Damascene process, will pose new challenges to both wire bond and flip chip interconnect technologies from process, metallization, and reliability perspectives. Owing to advances in equipment, materials, and processes; wire bonding continues to be offer a competitive advantage for ultra fine pitch (50um) applications. Wire bond interconnects using both Cu and Au wires on Cu or Cu/Al metallization have been proposed. However, multiple schemes for these metallization and the combination of these metallization along with the multitude of possible wire compositions have made this area widely explored yet little understood. These studies are further necessitated by the fact that the interconnect dimensions have now shrunk to under 30um diameter of the bonded ball and the under 400nm thickness of the silicon metallization.

This project aims at the studying the interactions between the new silicon metallization, the wire compositions including the dopants, and the functionality and reliability of the interconnection. Silicon metallization will include Cu, Al, Au deposited by evaporation, electroplating, electroless plating, as well as other novel processes that may be a combination of the above. Wire types will include Cu and Au with dopants such as Pd, Hf, Sc, Y, Gd, and Ce, amongst others. The interconnect process will be optimized using design of experiments and the reliability of the samples will be tested using accelerated life time testing such as temperature cycling, temperature humidity with and without bias, and high temperature storage. The inter-metallics forms will be identified using TEM, SEM, and electron backscattering diffraction, and surface analysis techniques.

The effect of dopants, wire composition, silicon metallization, in the formation and growth of the inter-metallics will be investigated. The growth kinetics of the inter-metallics and the strengthening mechanisms will be studied and correlated back to the effect of dopants and strengthening mechanisms as well as reliability of the interconnections.