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Nano-Rare-Earth Materials for Sub-45nm Nano-Electronic Devices
Investigators: Prof Lee Pooi See, Prof Gan Chee Lip and A/P Alfred Tok
Introduction
The purpose of the present project is to address the CMOS miniaturization challenges via the advanced materials and processing route. The application of rare-earth materials is employed to address both the short term and long term materials issues for sub-45 nm technologies.
High k dielectric gate materials
From the ITRS 2003 roadmap, 45nm CMOS technology is rapidly approaching. Attention is required immediately as the present SiO2 gate insulator will face tunneling leakage and dielectric breakdown problems. The team aims to develop high k dielectric materials which are also compatible to the substrate. The first challenge is on the interface engineering between the gate dielectrics and the substrate. Cost effective method for the epitaxial growth of complex rare-earth oxides as buffer layers is proposed. The next complementary study will be the material synthesis and formation of high k dielectrics on the substrate. Rare-earth based materials, such as La, Lu, Pr, which show excellent dielectric properties, will be employed and mechanistic material chemistry will be examined to facilitate the investigation.
Nano-interconnects
Along with the decrease in feature size, interconnects will also pose increasing difficulties. Limitation to lithography resolution is also rapidly approaching. The present work aims to address this issue via the use of nano-wires. This involves the synthesis of highly ordered self assembled nano-porous channels to serve as template for deposition of nanowires as interconnects with dimension beyond the limits of lithography. The template also serves as a platform for the team to introduce complex rare-earth silicide as interconnect materials. This involves a novel process where nano-particulate silicides will be electrophoretically deposited (EPD) onto the template to form nano-silicide-wires. Silicide materials are noted to possess comparatively low resistivity and rare-earth silicide compounds are hence attractive new materials with huge potential in this application.
Along with the decrease in feature size, interconnects will also pose increasing difficulties. Limitation to lithography resolution is also rapidly approaching. The present work aims to address this issue via the use of nano-wires. This involves the synthesis of highly ordered self assembled nano-porous channels to serve as template for deposition of nanowires as interconnects with dimension beyond the limits of lithography. The template also serves as a platform for the team to introduce complex rare-earth silicide as interconnect materials. This involves a novel process where nano-particulate silicides will be electrophoretically deposited (EPD) onto the template to form nano-silicide-wires. Silicide materials are noted to possess comparatively low resistivity and rare-earth silicide compounds are hence attractive new materials with huge potential in this application.
Quantum dots
After 2010, it is predicted that gate length less than 20 nm will be in production. Nevertheless, issues of power dissipation will persist, and may become the most serious issues in CMOS development. In that aspect, quantum dot is predicted to form the basis of the next generation of smaller, faster and lower power devices. However, the fabrication of quantum dots remains to be a great challenge in both the dimensional and cost aspects. In the present work, a new fabrication technique, electrostatic atomization, will be employed to address this nano-fabrication challenge. Preliminary work has shown that this technique is simple, cost effective and promising to deposit ordered pattern with high resolution.
